`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080
//
// CSE141L Lab 2, Part 1: Fetch Datapath
// University of California, San Diego
// 
// Written by Donghwan Jeon, 4/10/2007
// Updated by Sat Garcia, 4/8/2008
//

// sign extention unit
//
// parameters:
// 	IN: data width for the input
// 	OUT: data width for the output
//

module signext#(parameter IN=5, OUT=10)
(
    input   [IN-1:0]    d_i,
    output  [OUT-1:0]   d_o
);
	wire [OUT-1 : 0] sign_ext_0, sign_ext_1;
	assign sign_ext_0 = {{OUT-IN{1'b0}}, d_i[IN-1:0]};
	assign sign_ext_1 = {{OUT-IN{1'b1}}, d_i[IN-1:0]};
	
	reg [OUT-1:0] d_next;
	
	always_comb
		begin
			if(d_i[IN-1])
				d_next = sign_ext_1;
			else
				d_next = sign_ext_0;
		end
		
	assign d_o = d_next;
endmodule
